The invention relates to an integrated semiconductor memory configuration having a plurality of identical memory cells.
Each of the memory cells has a selection transistor having a drain region, a source region, and a gate. A storage capacitor of the memory cell has a first electrode, a second electrode and also a storage dielectric provided between the two electrodes.
The invention further relates to a method of fabricating an integrated semiconductor memory configuration having a plurality of identical memory cells.
In the case of a memory configuration of this type, additional space for interconnection or wiring is available on a main surface of the insulation layer above the selection transistors.
A memory configuration of this general type is disclosed in the German Published Patent Application DE 38 40 559 A1. The memory configuration described therein has a storage capacitor which is provided below a source region. The storage capacitor is conductively connected to the source region by a first electrode. A second electrode of the storage capacitor is connected to a common plate provided below the source region.
The German Published Patent Application DE 39 31 381 A1 describes a memory configuration having switching elements provided in a substrate below selection transistors. These switching elements may be embodied e.g. as storage capacitors connected by a first electrode to a source region of a selection transistor and by a second electrode to a common plate embodied as a buried interconnection plane.
The U.S. Pat. No. 4,794,434 discloses a memory configuration having a number of selection transistors whose respective source region is connected to a first electrode of a storage capacitor. The storage capacitor is situated in a substrate below the source region, and the second electrode below the source region is formed by a conductive substrate region which is electrically insulated from the source region.
The U.S. Pat. No. 5,309,008 describes a memory configuration having a number of selection transistors each having a source region which is connected to a first electrode of a storage capacitor. The storage capacitors are situated in a substrate in which also the source regions are provided. A second electrode of the storage capacitors is connected to a common plate provided below the source regions.
A disadvantage of the conventional memory configurations is the spatial configuration of the storage capacitors, which have to be fabricated prior to the selection transistors in the course of the production process. Particularly when special storage dielectrics, such as ferroelectric storage dielectrics, are used, contamination of the semiconductor process employed for fabricating the selection transistors can occur as a result of using these storage dielectrics.
It is accordingly an object of the invention to provide a semiconductor memory configuration, which overcomes the abovementioned disadvantages of the heretofore-known semiconductor memory configurations of this general type and in which additional space is available for interconnections on a main surface of the memory configuration, and which furthermore can easily be fabricated using conventional method steps.
A further object of the invention is to provide a method for fabricating the semiconductor memory configuration according to the invention.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory configuration, comprising:
a) a semiconductor body having a first side and a second side;
b) an insulation layer formed on the first side of the semiconductor body, the insulation layer having a cutout formed therein, the cutout having a side surface;
c) a common plate formed on the second side of the semiconductor body; and
d) a memory cell including
a selection transistor having a drain region formed in the semiconductor body, a source region formed in the semiconductor body and disposed between the cutout in the insulation layer and the common plate, and a gate formed in the insulation layer;
a storage capacitor provided on the side surface of the cutout, the storage capacitor having a first electrode connected to the source region of the selection transistor, a second electrode connected to the common plate, and a storage dielectric disposed between the first electrode and the second electrode.
In accordance with another feature of the invention, the storage dielectric has ferroelectric properties.
In accordance with yet another feature of the invention, the storage dielectric has a dielectric constant of greater than 10.
In accordance with a further feature of the invention, the storage dielectric is an oxidic dielectric and in particular SBTN SrBi2 (Ta1xe2x88x92xNbx) 2O9, SBT SrBi2Ta2O9, PZT (Pb, Zr) TiO3, BST (Ba, Sr)TiO3, or ST SrTiO3.
In accordance with another feature of the invention, the cutout is formed centrally over the source region.
In accordance with yet another feature of the invention, a conductive connection element extends downward through the source region and the semiconductor body and connects the second electrode to the common plate.
In accordance with a further feature of the invention, the storage dielectric extends downward through the source region and the semiconductor body to the common plate and surrounds the conductive connection element.
In accordance with another feature of the invention, the storage dielectric and the second electrode extend downward through the source region and the semiconductor body to the common plate and enclose the conductive connection element.
In accordance with yet another feature of the invention, an insulation collar extends downward through the source region and the semiconductor body to the common plate and encloses the conductive connection element in a region of the source region and in a region of the semiconductor body.
In accordance with another feature of the invention, the common plate and the semiconductor body form an integral semiconductor substrate, the common plate being a doped region of the semiconductor substrate.
With the objects of the invention in view, there is also provided a method of fabricating a semiconductor memory configuration, the method which comprises:
providing a semiconductor body having a first side and a second side;
providing an insulation layer on the first side of the semiconductor body;
fabricating a common plate on the second side of the semiconductor body;
doping the semiconductor body for forming a source region and a drain region of a selection transistors;
providing a gate for the selection transistor in the insulation layer;
etching the insulation layer for forming a first cutout in the insulation layer over the source region;
applying a first electrode on a side surface of the first cutout;
further etching the first cutout through the source region and the semiconductor body as far as to the common plate for forming a second cutout;
depositing a storage dielectric and a second electrode on the first electrode and on a side surface of the second cutout; and
filling an interspace within the second electrode with conductive material for fabricating a conductive connection element.
With the objects of the invention in view there is furthermore provided a method of fabricating a semiconductor memory configuration, the method which comprises:
providing a semiconductor body having a first side and a second side;
providing an insulation layer on the first side of the semiconductor body;
fabricating a common plate on the second side of the semiconductor body;
doping the semiconductor body for forming a source region and a drain region of a selection transistor;
providing a gate for the selection transistor in the insulation layer;
etching the insulation layer for forming a first cutout in the insulation layer over the source region;
applying a first electrode on a side surface of the first cutout;
depositing a storage dielectric and a second electrode on the first electrode;
further etching the first cutout through the source region and the semiconductor body as far as to the common plate for forming a second cutout;
depositing an insulation layer over the second electrode and on a side surface of the second cutout;
removing the insulation layer from a region of the second electrode for fabricating an insulation collar; and
filling an interspace within the second electrode and the insulation collar with conductive material for fabricating a conductive connection element.
In accordance with another mode of the invention, the step of fabricating the common plate includes introducing a dopant into the semiconductor body by deep implantation.
In accordance with yet another mode of the invention, a barrier layer is applied over the source region prior to the step of applying the first electrode or prior to the step of depositing the storage dielectric.
In accordance with a further mode of the invention, the barrier layer is formed of TiN, WN, WTiN, or TaN.
The object of the invention is in particular achieved by providing the storage capacitor on a side surface of a cutout in the insulation layer over the source region.
In the case of the semiconductor memory configuration described, it is possible to use in a simple manner prefabricated configurations, which include selection transistors, for fabricating the memory configuration. The storage capacitors can be fabricated at a location that is different from the location where the selection transistors are fabricated. The risk of contaminating the semiconductor process employed for fabricating the selection transistors is thus avoided.
One embodiment of the invention provides for the use of ferroelectric materials as the storage dielectric. Such ferroelectric materials afford the advantage that the information which is stored in the form of an electric charge in the storage capacitors is preserved after failure of a supply voltage. A further advantage is that the information does not have to be refreshed at regular intervals. Such a refreshing is generally necessary because of leakage currents that occur in the case of customary semiconductor memory configurations, which use a dielectric having paraelectric properties.
The ferroelectric properties of most of the ferroelectric materials which are known to date and are appropriate for storage dielectrics of this type are temperature-dependent. These ferroelectric materials have a ferroelectric behavior below a temperature which is characteristic for them, while they have a paraelectric behavior above this characteristic temperature, the dielectric constant in the paraelectric state being significantly higher than the dielectric constants of storage dielectrics used to date. The temperature below which ferroelectric properties are established is very low in the case of some ferroelectric materials, with the result that, from a technical standpoint, these ferroelectric materials can be used only in the paraelectric state, their dielectric constant in the paraelectric state in each case being above 10, preferably above 100.
One embodiment of the invention provides for the storage dielectric to have a dielectric constant of greater than 10. Materials for storage dielectrics of this type are, for example, the above-mentioned ferroelectric materials which are used at a temperature above their respective characteristic temperature.
One embodiment of the invention provides for the storage dielectric to be an oxidic dielectric. The class of oxidic dielectrics includes, by way of example, SBTN SrBi2 (Ta1xe2x88x92xNbx) 2O9, SBT SrBi2Ta2O9, PZT (Pb, Zr) TiO3, BST (Ba, Sr)TiO3 or ST SrTiO3. The formula (Pb, Zr)TiO3 stands for PbxZr1xe2x88x92xTiO3. The proportion of Pb and Zr in this substrate can vary, the ratio of Pb and Zr critically determining the temperature behavior of this dielectric, that is to say determining the temperature below which the substrate has ferroelectric properties or above which the substrate has paraelectric properties. The formula (Ba, Sr)TiO3 stands for BaxSr1xe2x88x92xTiO3, wherein the temperature behavior of this substrate can be substantially determined by way of the ratio of Ba to Sr. The list of substances mentioned is in no way complete. The selection of one of the substances as the storage dielectric mainly depends on processing factors during the fabrication method, but also on factors during the use of the semiconductor memory configuration, for example the ambient temperature.
If such materials having a high dielectric constant are used, it is possible to fabricate storage capacitors with sufficient capacitances in conjunction with a small capacitor area.
The cutout in the insulation layer is preferably provided centrally over the source region, as is proposed in a further embodiment of the invention.
A further embodiment of the invention provides for the second electrodes of the respective memory cells to be connected to the common plate by a conductive connection, which extends downward through the source region and the semiconductor body.
In order to insulate the conductive connection from the source region and the semiconductor body, one embodiment of the invention provides for the storage dielectric to extend downward through the source region and the semiconductor body as far as the common plate and to surround the conductive connection. The second electrode can also extend downward through the source region and the semiconductor body as far as the common plate, wherein the second electrode extends downward between the conductive connection and the storage dielectric.
A further embodiment of the invention provides for the conductive connection to be insulated from the source region and the semiconductor body by an insulation collar, which may for example be formed of a semiconductor oxide.
The common plate provided below the selection transistors may be a region of the semiconductor body, wherein the region is doped so that it has a sufficient electrical conductivity.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory configuration with a buried plate electrode and a method of fabrication such an integrated semiconductor memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.